The present application claims priority to Japanese Application No. P11-032253 filed Feb. 10, 1999 which application is incorporated herein by reference to the extent permitted by law.
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and more particularly to a method of manufacturing a semiconductor device of forming upper layer interconnections on a buried plugs comprising tungsten.
2. Description of the Related Art
Along with increasing degree of integration and refinement for semiconductor devices, it has become important for the introduction of a so-called borderless structure having no overlapping margin between connection holes and conductor interconnections. Usual conductor interconnections are not formed by a minimum design rule but formed by a design rule while considering overlap to connection holes or misalignment of conductor wires to connection holes above connection steps. Accordingly, as the progress of refinement, the integration degree is restricted by the overlapped portion. Accordingly, it is one of technical subjects for higher integration degree to provide a borderless structure of not deteriorating the device yield and the wiring reliability even if misalignment should occur.
Explanations are to be made for the related art with reference to the manufacturing step chart of FIG. 3. As shown in FIG. 3a, after forming lower layer interconnections 112 on an underlying insulating film 111, an interlayer insulating film 113 is deposited on the underlying insulating film 111 in a state of covering the lower layer interconnections 112 and then the surface is flattened. Subsequently, as shown in FIG. 3b, a resist film 114 having an opening pattern 114 used for fabrication of connection holes is formed on the interlayer insulation film 113. Then, using the resist film 114 as a mask, connection holes 115 in communication with the lower layer interconnections 112 are formed in the interlayer insulating film 113 by anisotropic dry etching.
Subsequently, after removing the resist film 114, as shown in FIG. 3c, reverse sputter cleaning is conducted using, for example, a magnetron sputtering device. Then, an adhesion layer 116 is formed to the inner wall of the connection holes 115 and on the interlayer insulation film 113 and then a tungsten film is formed over the entire surface as a burying metal to the connection holes by 115 by CVD process. Subsequently, an excess tungsten film and the adhesion layer 116 on the interlayer insulation film 113 are removed by using an entire surface etching back method by reactive ion etching, to form buried plugs 117 comprising a tungsten film
Then, as shown in FIG. 3d, a metal layer 118 for upper layer interconnections covering the buried plugs 117 is formed on the interlayer insulation film 113, for example, by magnetron sputtering. The metal layer 118 is prepared, for example, by forming, a titanium film formed to 200 nm thickness, a titanium nitride film to 20 nm thickness, an Al-0.5% Cu film to 500 nm thickness, titanium to 5 nm thickness, and then a titanium nitride film to 100 nm thickness successively from the lower side. Then, a resist film 119 as a mask for forming upper layer interconnections is formed by resist coating and lithographic technique.
Then, as shown in FIG. 3e, the metal layer 118 is etched by anisotropic dry etching using the resist film 119 as an etching mask, to form upper layer interconnections 120. As the condition for the anisotropic dry etching, boron trichloride (BCl3) (100 sccm) and chlorine (Cl2) (150 sccm) are used for the etching gas, and etching is conducted while at 40% overetching relative to just etching setting the pressure for the etching atmosphere at 1 Pa, the microwave power at 400 mA and the high frequency RF at 110 W.
Then, the resist film 119 is removed by an ashing treatment and a liquid chemical cleaning treatment. The ashing treatment is conducted by using a parallel plate type reactive ion etching apparatus, and using oxygen (O2) (flowrate: 3750 sccm) as the processing gas, while setting the process temperature at 250xc2x0 C., the pressure for the ashing atmosphere at 150 Pa, RF power at 900 W and the ashing time for 60 sec. The liquid chemical cleaning treatment comprises immersion in an amine type solvent for 15 min and cleaning by running water for 10 min.
However, in a case where the buried plugs are locally exposed upon liquid chemical treatment, electrochemical reaction occurs during the amine type organic solvent treatment under the effect of charges accumulated in aluminum during wiring fabrication to form buried plug 117b leaching tungsten. This is illustrated in FIG. 4. In the thus formed semiconductor device, since through hole (connection hole) resistance increases locally and electric conduction yield relative to the lower layer interconnections is lowered, the device yield is lowered. Further, even when tungsten leaches to such an extent as not causing conduction failure, it may be a worry for the degradation of reliability between the upper layer interconnections and the buried plugs (by electromigration, stress migration and the like).
The present invention provides a method of manufacturing a semiconductor device for overcoming the foregoing problems. A first manufacturing method for a semiconductor device comprises the steps of: forming upper layer interconnections on buried plugs formed in an insulating film, wherein the upper layer interconnections are patterned by etching, a surface of the buried plugs being partially exposed with no upper layer interconnections formed thereon; and plasma processing using an oxygen series gas with addition of a fluorine series gas is applied to the exposed surface of the buried plugs at least before removing a resist film used as an etching mask with an organic stripping liquid, thereby forming a protection film on the surface of the buried plugs.
According to the first manufacturing method, since the plasma processing is applied to the exposed surface of buried plugs by using an oxygen series gas incorporated with the fluorine series gas at least before removing the resist film used as the etching mask with the organic stripping liquid thereby forming the protection film on the surface of the buried plugs, the surface of the buried plugs is covered with the protection film even if the resist film is removed thereafter by the organic stripping liquid, the buried plugs are not leached out by electrochemical reaction with the organic stripping liquid. Accordingly, the present invention provides a method of forming interconnections for highly integrated semiconductor devices having stable device yield and high reliability.
A second manufacturing method of the present invention comprises a method of manufacturing a semiconductor device of forming upper layer interconnections on buried plugs formed in an insulating film, wherein the upper layer interconnections are patterned and formed by etching and plasma processing using a gas mainly comprising an inert gas is applied to the surface of the buried plugs formed being extended out of the upper layer interconnections at least before removing a resist film used as an etching mask with an organic stripping liquid, thereby eliminating static charges accumulated on the upper layer interconnections.
In the second manufacturing method, since the plasma processing is applied to the surface of the buried plugs formed being extended out of the upper layer interconnections by using a gas mainly comprising an inert gas at least before eliminating the resist film used as the etching mask with the organic stripping liquid, electrostatic charges accumulated on the upper layer interconnections are removed. Accordingly, even if the resist film is removed by the organic stripping liquid, electrochemical reaction with the organic stripping liquid less occurs and leaching of the buried plugs is suppressed. Accordingly, the present invention provides a method of forming interconnections for highly integrated semiconductor devices having stable device yield and high reliability.